Ohio University
School of Electrical Engineering and Computer Science
EE4143/5143 Design of Digital Circuits
Course Schedule, Spring 2017

Last Modified Thursday, January 10, 2017

Wk	Date	Required Video Lectures and Lab Material	Required Reading	Additional Reading	Homework
	The week begins on	Homework and lab reports are due at the end of the week.	Submit in time through Blackboard.	Late HW and computer assignments will lower the assignment grade as follows:	1 day late  -10% < 1 week  -25% < 1 month  -50% > 1 month  -75%
1	Jan 9	1. Digital versus Analog 2. Integrated Circuits 3. IC Spectrum 4. Lab Setup and Software Installation 5. Digital Circuits 1 6. Digital Circuits 2 7. Lab 1 Simulation with Aldec HDL	1. Download Evita, 2. Read the following Wikipedia articles: 3. Integrated Circuit Logic Family		1. Install lab software on your computer 2. Start on design proposals 3. Write a 1000 word essay on the technical superiority of digital electronics over analog electronics. Mention such topics as information processing, storage and communication.
2	Jan 16	1. Programmable IC Structure 2. ROMs 3. PLDs 4. FPGAs 5. ASICs 6. Programmable IC Choices 7. Evita Tutorial 2 8. VHDL Basic Concepts 9. VHDL Modeling Concepts 10. Lab 2 Full Adder Design Using Xilinx ISE WebPACK	1. Read sections 2.3-2.6 2. Format for design proposal 3. Sample final project design ideas	1. Read 2.1 - 2.9, 2. Read 3.1-3.6,	1. In a Word document, answer the following questions: a. What is the difference between FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device)? b. What roles do EDA, FPGA and CPLD play in digital design? 2. Finish lab1 send simulation waveforms, no report due. You are to submit a single Word document that includes Parts 1 and 2 of this assignment.
3	Jan 23	1. VHDL History 2. VHDL Structure 3. Entity 4. Architecture 5. Processes 6. Evita Tutorial 3 7. VHDL Tutorial on Structural Design using Components and Packages 8. Concurrent and Sequential Statements 9. Sequential Statements 10. If, Case, Loop, Next, and Exit Statements 11. Lab 3 Structural Design in VHDL using Components and Packages	Read sections 3.1, 3.2, 3.3 (without 3.3.3-3.3.5)	1. Read 4.1-4.5,	1. Answer the following questions from Chapter 3 in your textbook: Questions 3.1- 3.4 and 3.9. 2. Finish lab2. Provide a written Lab Report for this week’s lab assignment (maximum 3 pages). What can you infer from, the Outputs in the Console window and the Design Summary tab? What are the factors that come into picture in selecting a FPGA for your design implementation? You are to submit a single Word document that includes Parts 1 and 2 of this assignment. More information regarding lab reports can be found on the Lab Report Guidelines webpage.
4	Jan 30	1. Description of Design Styles 2. VHDL Synthesis versus Simulation 3. Concurrency in VHDL 4. Evita Tutorial 6 5. Null, Return, and Assertion Statements 6. Lab 4: Creating a 4-bit Adder Using the Xilinx CORE Generator	Read sections 3.3.3-3.3.5	1. Read 4.6-4.12,	Answer question 3.5 (chapter 3) from your textbook. In no more than 1000 words, explain how VHDL implements parallelism (concurrency) through its simulation cycles. Finish lab3. Provide a written Lab Report for this week’s lab assignment (maximum 6 pages). Write your name and selected topic for the final project in this Google document.
5	Feb 6	1. VHDL Identifiers 2. Reserved Words 3. Data Objects 4. VHDL Types 5. Concurrent an selected signal assignments 6. Component instantiation 7. Generate and block statements 8. Lab5: Top-Down VHDL Design for Xilinx FPGAs	Read section 3.4	1. Read 5.1-5.8,	1. Submit project proposal for instructor approval. Format for design proposal. 2. Finish lab4. Provide a written Lab Report for this week’s lab assignment (maximum 4 pages). Include a snapshot of your board that shows the output for a selected input A=”0011” and B=’’0110’’.
6	Feb 13	1. Code Reusability 2. Procedures and functions 3. Libraries and packages 1 4. Libraries and packages 2 5. Evita Tutorial 8 6. Subprogram 7. Package and resolution function 8. Subprogram overloading, return values and type casting 9. Design unit, generics 10. Configuration specification, Configuration declaration, library	Read sections 6.2.1 and Chapter 7	1. Read 6.1-6.8	Question 7.1 (Skahill, Chapter 7) Question 7.5 (Skahill, Chapter 7) Write a procedure to perform 8-bit even parity check. 4. Begin working on Lab 5.
7	Feb 22	Midterm		Review chapters 1-7	1. Revise all the material contained in modules 1 to 6. 2. past midterm solution
8	Feb 27	1. Combinational Logic Structure 1 2. Combinational Logic Structure 2 3. Combinational Logic Design 4. VHDL Operators 5. Evita Tutorial 7 6. A design case 7. A test bench 8. Simulation results 9. Another test bench	Read section 4.3	1. Read 11.1-11.6	1. Answer the following questions from your textbook: Chapter 4: Questions 4.1 – 4.6 2. Finish lab5. Provide a written Lab Report for this week’s lab assignment (maximum 5 pages).
9	March 6	Spring break		Spring break	Spring break
10	March 13	1. Sequential Circuits 2. Modeling Flip Flops 3. Resets Presets 4. Tristate Output 5. Bidirectional Signals 6. Evita Tutorial 4 7. Finite state machines - introduction 8. Writing VHDL for FSM 9. FSM initialization 10. FSM output 11. FSM synthesis	Read section 4.4	1. Read 9.1-9.5	Write VHDL code for the following: D-flip-flop T-flip-flop 8-bit wide serial shift register with D-flip-flops Question 4.13 (Skahill, Chapter 4) Question 4.15 (Skahill, Chapter 4)
11	March 20	1. Silicon VLSI material 2. VLSI Design 3. VLSI Layout 4. VLSI Fabrication 5. Digital Circuits 3 6. Digital Circuits 4	1. 2. Read two articles: CMOS Semiconductor device fabrication 3. Read Quiz1 ahead of watching video on VLSI manufacturing process	Silicon Run I (You will be directed to the ALICE Catalog). You will need to login with your Ohio Blackboard credentials to view this resource.	Answer the following questions: List the steps needed for making a complete monolithic silicon integrated circuit. Which semiconductors, other than silicon, are commercially used for making ICs? Submit a behavioral/structural description of your final design project. Submit answers to Quiz 1
12	March 27	1. MOS Basics 2. MOS Capacitor 3. MOSFET Structure 4. MOSFET Operation 5. Design Metrics Part 1 6. Design Metrics Part 2 7. The Wires Part 1 8. The Wires Part 2 9. The Wires Part 3 10. The Wires Part 4	1. 2. 3. 4. Read the article: MOSFET 5. Read Quiz 2  ahead of video on fabrication, packaging, and test	1. Read 2.3, Silicon Run II (You will be directed to the ALICE Catalog). You will need to login with your Ohio Blackboard credentials to view this resource.	A silicon n-channel MOSFET has a length of 100 nm and a width of 250 nm. It has an oxide thickness of 10 nm. a. Calculate the MOS oxide capacitance and the drain current at a gate-source voltage of 3 volts with a drain-source voltage of 6 volts if the threshold voltage is +2 volts. b. Take electron mobility in silicon to be 1100 cm2/v.sec and the permittivity of silicon to be 1x10-10 Farad/meter. c. Elmore delay (in the attached document) d. Submit answers to Quiz 2
13	April 3	1. Digital Logic Gates 2. CMOS Inverter 3. CMOS Logic Gates 4. Static CMOS compound gates (ppt) 5. Transient Behavior, Diffusion Capacitance (ppt) 6. CMOS Inverter Characteristic, VTC, Noise Margins, Delays, Power Dissipation	1. Read the article: Inverter (Logic Gate).	1. Read 3.2-3.3 pp.109-149 2. Read 3.3, 3.5,3.6, 3.2.4, 3.3.4, 4.1, 4.2	Part 1: Power Dissipation Problem The switching power dissipated by a CMOS inveter is given by ½ CV^2f. Here C is the capacitance of the inverter’s input, V is the supply voltage and f is the operating frequency. Given a circuit with 100 inverters (or inverter equivalent CMOS logic gates), operating at 5 volts supply voltage and 10 MHz clock frequency, calculate its electrical power dissipation. Take the capacitance of each inverter input as 2 femto Farad (2x10^-15 Farad). Part 2: Inverter sizing (in the attached document) Part 3: Final Project. Submit the final design project simulation results.
14	April 10	1. IC Layout Intro 2. CMOS Layout 3. Stick diagrams and Layout (ppt)	1. Read the paper: CMOS Transistor Layout KungFu	1. Read 3.3.5 2. Read 4.2.1-4.2.3	1. Provide a sketch of each of following: CMOS layout for the XOR function CMOS layout for a two 2-input AND gates with their outputs connected to a 2-input OR gate. Do this using both AND and OR gates and then using only NAND gates. 2. Draw a stick diagram of each of the following. 2-input NOR gate 2-input AND gate
15	April 17	1. Stick Diagrams 2. Cell Partitioning Floor Planning	1. Final Project demonstration in lab. 2. Designs must be mapped to the Xilinx board and tested 3. TA must check and approve your deign		1. Cell Layout (in the attached document) 2. Part 2: Final Project. Submit your Final Project report. Format for Final Project report.

Notes: Reading assignments are marked in different colors depending on the text book:

Chapter sections in green are from the text by Kevin Skahil, “VHDL for Programmable Logic”, Dorling Kindersley Pvt Ltd, 2006.

Chapter sections in black and white are from the text by J. M. Rabaey, A. Chandrasakasan, B. Nikolic "Digital Integrated Circuits - A Design Perspective", Prentice Hall, 2003.

Chapter sections in blue are from the text by K.C. Chang, "Digital Design and Modeling with VHDL and Synthesis", IEEE Computer Society Press, 1997.

Homework are due by the date indicated.

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Note:
Most of the presentation slides are adapted from "Digital Integrated Circuits - Instructor Resources" at http://bwrc.eecs.berkeley.edu/IcBook/  see also http://infopad.eecs.berkeley.edu/~icdesign, Copyright 2002 UCB.